1. Field of the Invention
The present invention is related to a non-volatile memory and, more particularly to a non-volatile memory having a function of dynamic RAM and a function of EEPROM.
2. Description of the Related Arts
Generally, semiconductor memory devices include a non-volatile memory (such as EEPROM) in which stored contents are retained after a power supply is turned off and a volatile memory (such as RAM) in which stored contents disappear when the power supply is turned off. EEPROM of a non-volatile memory can store data for a long time even after a power supply is turned off, but it is not suitable for frequently rewriting the data because it takes a lot of time for writing/erasing the data and the number of writing/erasing times is limited. On the other hand, RAM of a volatile memory takes only a short time for rewriting data and has no limitation to the number of rewriting times, but lets the stored data disappear when a power supply is turned off.
Therefore, as a semiconductor memory capable of rewriting the data frequently and retaining the rewritten data for a long time, there has been proposed a non-volatile RAM (NVRAM) which is a combination of EEPROM cells and RAM cells.
For example, Japanese Unexamined Patent Publication (Kokai) No. HEI 2(1990)-240960 discloses a semiconductor device in which EEPROM and DRAM are combined as NVRAM cells.
This semiconductor device is made up of a plurality of cells, each cell including a DRAM portion and an EEPROM portion. As shown in a cell circuit diagram of FIG. 18 and a cross-sectional cell structure of FIG. 19, a DRAM portion includes one MOS transistor (hereafter referred to as transistor T) and one capacitor C having a stack structure. The EEPROM portion includes one FLOTOX-type MOS transistor (hereafter referred to as transistor MT) on a semiconductor substrate.
In the transistor T, a word line is connected to a gate electrode 27, and a bit line is connected to a drain diffusion layer 21. The capacitor C has a stack structure in which a dielectric film 29 is sandwiched between a plate capacitor electrode 26 and a storage node (control gate) 25. The storage node 25 is connected to a source diffusion layer 23 of the transistor T. The transistor MT includes a floating gate 24 for storing the data for a long time, a tunnel dielectric film 28 disposed between the floating gate 24 and the source diffusion layer 22, and also includes the above-mentioned control gate 25. The drain diffusion layer of the transistor MT is connected to the source diffusion layer 23 of the transistor T.
The operation of a conventional semiconductor device constructed as a combination of EEPROM cells and DRAM cells in the manner shown above is as follows. In frequently rewriting data, the device is operated as a DRAM (DRAM operation). When a power supply is to be turned off or the data need to be stored for a long time, the data are transferred from a DRAM portion to an EEPROM portion in a lump to be stored in the EEPROM portion (storing operation). When the power supply is turned on, the data stored in the EEPROM portion are transferred back and stored in the DRAM portion (recalling operation).
However, this semiconductor device is accompanied by a drawback that, since it is made of DRAM portions and EEPROM portions, it is difficult to reduce the area on the semiconductor substrate occupied by the semiconductor device due to the requirement of area occupied by each portion, rendering the device unsuitable for large scale integration.
Also, Japanese Unexamined Patent Publication (Kokai) No. HEI 6(1994)-244384, for example, discloses a composite memory cell which is a combination of DRAM cells and non-volatile memory cells as NVRAM cells.
The composite memory cell is constructed as shown in a cell circuit diagram of FIG. 20 and a cross-sectional cell structure of FIG. 21. On one side of a substrate 35 for forming elements, there are formed a non-volatile memory cell including a floating gate 30 and a control gate 31 and data storage portions 32, 33, 34 of the DRAM cell. Above these cells, a support substrate 38 is bonded. On the other side of the substrate 35, there are formed a gate electrode 37, a channel region 36A and source/drain regions 36B constituting the DRAM cell.
This composite memory cell has an advantage that the occupied area of the substrate can be reduced compared with the above mentioned semiconductor device because gate regions of the DRAM cell and the non-volatile memory are stacked in a vertical direction with the channel region disposed therebetween. However, this composite memory cell is accompanied by a drawback that the structure and the manufacturing process are complicated because it requires a step of bonding a support substrate 38 above the non-volatile memory cell and the data storage portions of the DRAM cell and a step of removing a part of the substrate 35 for forming elements.
Further, Japanese Unexamined Patent Publication No. HEI 6(1994)-5801, for example, discloses a one-transistor non-volatile DRAM. This memory has a structure shown in a circuit diagram of FIG. 22 and a cross-sectional structure of FIG. 23. As shown, the memory includes a capacitor C and a transfer transistor TT formed in a semiconductor substrate 41. The capacitor C includes a storage node 42, a dielectric film 43 and an upper electrode 44. The transfer transistor T includes a source 45, a drain common to the storage node 42, a control gate 46 and floating gate 47a, 47b formed in a two-layer structure.
In this memory, data stored in the capacitor are transferred to the floating gate 47b by allowing electrons to pass by tunnel current between the floating gate 47b near the semiconductor substrate 41 and the storage node (drain) 42 of the capacitor C.
Specifically, in order to transfer the data from the capacitor C to the floating gate 47b, a voltage of +15V is applied to all word lines WL, and all bit lines BL are grounded. If a storage state in the capacitor C is data -"1" corresponding to a voltage of -5V of the capacitor C, electrons pass by tunnel current from the drain 42 to the floating gate 47b via tunnel oxide because an electric field in the transfer transistor TT near the capacitor C is sufficiently high. Since a capacitance of the capacitor C is extremely higher than that of the control gate 46, it is sufficient to charge the floating gate 47b into negative voltage. Thus, the voltage of -5V stored in the capacitor C is transferred to the floating gate 47b. On the other hand, if a voltage of the capacitor C is 0V indicating data "0", an electric field in the interlayer dielectric film is not sufficiently strong to allow electrons to pass by tunnel current into the floating gate 47b. As a result, the electrons are not injected into the floating gate 47b, keeping the floating gate 47b uncharged. Accordingly, the data stored in the capacitor C during a previous DRAM mode operation are transferred perpetually into the floating gate 47b and remain there until a power is restored and a recalling/erasing mode is activated (non-volatile storage). Thus, since a voltage of 15V is applied to the word line WL, the transfer transistor T is in an OFF-state and a channel layer is not formed.
Generally, writing characteristics of a non-volatile memory is determined by a potential difference between source/drain regions and a word line. However, in the case of the above memory cell, positive holes are generated in the drain 42 as a result of injection of electrons into the floating gate 47b. Moreover, since the drain 42 is in a floating state, the positive holes are accumulated in the drain 42. Therefore, the potential of the drain 42 decreases, so that the potential difference between the drain 42 and the word line WL grows smaller in accordance with the writing operation. As a result, there arises a problem that the writing characteristics vary widely.
At the time of erasing, a voltage of -20V is applied to a selected word line WL and a voltage of 0V is applied to all bit lines BL to erase data stored in the floating gate 47. This allows the electrons to pass by tunnel current into the drain 42 to remove the electrons remaining in the floating gate 47. Thus, since the voltage of -20V is applied to the word line WL, the transfer transistor TT is in an ON-state. The electrons in the floating gate 47 are drawn into the drain 42 by the potential difference between the drain 42 and the word line WL provided by supplying to the drain 42 via the channel layer the voltage applied to the bit line BL in which a channel region is formed. Here, since a tunnel oxide film is formed only on a drain side, the electrons are drawn into the drain. As a result, there arises a problem that, since a drain voltage decreases due to "ON" resistance, a source voltage must be raised by an amount corresponding to the "ON" resistance.